Signal processing device, signal processing method, delta-sigma modulation type fractional division pll frequency synthesizer, radio communication device, delta-sigma modulation type d/a converter

ABSTRACT

A fractional frequency divider ( 28 ) includes a latch ( 31 ) for holding frequency division data, a ΔΣ modulator ( 33 ), a digital dither circuit ( 32 ) for receiving a digital input F representing fraction part of the frequency division data from the latch ( 31 ) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator ( 33 ), and circuit means ( 34  through  38 ) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator ( 33 ). The digital dither circuit ( 32 ) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator ( 33 ) receives a particular F value (e.g., F=2 n−1 ).

TECHNICAL FIELD

The present invention relates to a signal processing device, a signalprocessing method, a delta-sigma modulation type fractional frequencydivision PLL frequency synthesizer, a radio communication device and adelta-sigma modulation type D/A converter.

BACKGROUND ART

A delta-sigma (ΔΣ) modulator has a circuit configuration which performsfeedback of quantization noise generated in an output to an input via adelayer and sometimes is called “sigma-delta (ΣΔ) modulator” or “noiseshaper” because of its function of biasing quantization noise to thehigh frequency band.

When a frequency synthesizer including a phase locked loop (PLL) is usedfor a radio communication device such as a cellular phone, in order toensure many available bands, it is required to change an outputfrequency with a smaller step size than the frequency of a referencesignal. As a frequency synthesizer to meet this requirement, a ΔΣmodulation fractional frequency division PLL frequency synthesizer hasbeen known. An exemplary ΔΣ modulation fractional frequency division PLLfrequency synthesizer is described in U.S. Pat. No. 5,070,310. In thePLL frequency synthesizer, a fractional frequency divider forfrequency-dividing an output of a voltage control oscillator to feedbackthe output to a phase comparator includes a ΔΣ modulator and a digitalvalue F representing fraction part (non-integer part) of frequencydivision data is given to the ΔΣ modulator.

Moreover, a high accuracy digital/analog (D/A) converter including a ΔΣmodulator, i.e., a ΔΣ modulation D/A converter is used for an audiodevice and the like.

DISCLOSURE OF INVENTION

With the ΔΣ modulation fractional frequency division PLL frequencysynthesizer, assuming that the frequency of the reference signal givento the phase comparator is Fref and the digital value F representingfraction part of the frequency divided data is binary data of n (n is aninteger), an output frequency step size equal to Fref×(F/2^(n)) can beachieved. However, it has been pointed out as a problem that as a resultof concentration of quantization noise at a particular frequency whenthe ΔΣ modulator receives a particular F value (e.g., F=2^(n−1)), aspurious signal is generated. Then, in a known manner, n takes a largevalue (Fref=26 MHz, n=24 in the above-described United State Patent) andF, which may be a problem, is substituted by F+1 or F−1. Accordingly,two problems, i.e., (1) a problem in which circuit scale is increasedand (2) a problem in which an output frequency is slightly shifted froma desired frequency, arise.

With a ΔΣ modulation D/A converter, spurious problems arise such asthose described above, which depends on a digital input of ΔΣ modulator.

An object of the present invention is to suppress concentration ofquantization noise at a particular frequency.

To achieve the above-described object, the present invention uses asignal processing device which has a configuration including, inaddition to a delta-sigma modulator, a dither circuit, located between adigital input and the delta-sigma modulator, for selectively supplying adigital signal which has been discretely changed from the digital inputand of which a time average corresponds to the digital input. Thus, evenif a bit width of the digital input is not increased, concentration ofquantization noise at a particular frequency can be suppressed.

The signal processing device can be applied to a fractional frequencydivision PLL frequency synthesizer, an A/D converter, a radiocommunication device and the like.

According to the present invention, a dither circuit, located between adigital input and the delta-sigma modulator, for selectively supplying adigital signal which has been discretely changed from the digital inputand of which a time average corresponds to the digital input is adopted.Thus, even if a bit width of the digital input is not increased,concentration of quantization noise at a particular frequency can besuppressed. Therefore, a known spurious problem can be dissolved andalso a desired output frequency can be obtained.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating the configuration of a cellularphone according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the internal configuration of aΔΣ modulation fractional frequency division PLL frequency synthesizershown in FIG. 1.

FIG. 3 is a block diagram illustrating the internal configuration of adigital dither shown in FIG. 2.

FIGS. 4(a) and 4(b) are timing charts describing the operation of thedigital dither circuit shown in FIG. 3.

FIG. 5 is a graph showing simulation results for quantization noise inthe ΔΣ modulation fractional frequency division PLL frequencysynthesizer of FIG. 2.

FIG. 6 is a block diagram illustrating the configuration of a ΔΣmodulation type D/A converter according to an embodiment of the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION <The Configuration of aCellular Phone>

FIG. 1 is a block diagram illustrating a cellular phone (radiocommunication device) to which a ΔΣ modulation fractional frequencydivision PLL frequency synthesizer according to the present invention isapplied. The cellular phone shown in FIG. 1 includes a ΔΣ modulationfractional frequency division PLL frequency synthesizer 2, a frequencydivider (DIV) 3, a modulator/demodulator (mixer) 4, a gain controlamplifier (GCA) 5, a low-pass filter (LPF) 6, an analog/digital (A/D)converter 7, an digital/analog (D/A) converter 8, a base band LSI 9, aspeaker 10, microphone 11, a changing switch 12, an antenna 13, a lownoise amplifier 14 and a driver amplifier 15. Fo denotes an outputsignal of the ΔΣ modulation fractional frequency division PLL frequencysynthesizer.

<The Configuration of the PLL Frequency Synthesizer 2>

FIG. 2 is a block diagram illustrating an internal configuration of theΔΣ modulation fractional frequency division PLL frequency synthesizer 2of FIG. 1. Referring to FIG. 2, the PLL frequency synthesizer 2 includesa reference frequency source 21, a coupling capacitor 22, a referencefrequency divider (R) 23, a phase comparator (PD) 24, a charging pump(CP) 25, a low-pass filter (LPF) 26, a voltage control oscillator (VCO)27, and a fractional frequency divider 28. The phase comparator 24, thecharging pump 25, the low-pass filter 26, the voltage control oscillator27 and the fractional frequency divider 28 together form a phase lockedloop (PLL). The fractional frequency divider 28 is a pulse swallowfrequency divider and includes a latch 31, a digital dither circuit 32,a ΔΣ modulator 33, an adder 34, a prescaler 35, an A counter 36, an Ncounter 37, and a modulus controller 38.

<The Operation of the PLL Frequency Synthesizer 2>

In the ΔΣ modulation fractional frequency division PLL frequencysynthesizer 2 of FIG. 2, the fractional frequency divider 28 performsfrequency division of an output signal Fo of the voltage controloscillator 27. A comparative signal Fdiv obtained through the frequencydivision is returned to the phase comparator 24. The phase comparator 24detects a phase difference between the reference signal Fref and thecomparative signal Fdiv and gives a voltage pulse having a pulse widthaccording to the phase difference to the charging pump 25. The chargingpump 25 becomes in one of three states, i.e., a state in which a currentis discharged, a state in which a current is drawn, and a state in whichimpedance is high, according to an output of the phase comparator 24 andgives a charging pump output current to the low-pass filter 26. Thecharging pump output current is smoothed and voltage-converted by thelow-pass filter 26 to be a control voltage of the voltage controloscillator 27.

<The Operation of the Fractional Frequency Divider 28>

Next, the operation of the fractional frequency divider 28 of FIG. 2will be described. (P+1) frequency division by the prescaler 35 isexecuted to the output signal Fo of the voltage control oscillator 27and then is received by the A counter 36 and N counter 37. The A counter36 counts the output signal Fo of the voltage control oscillator 27,which has been (P+1) frequency-divided, at A times and then outputs apulse. In response to this, the modulus controller 38 changes afrequency division number for the prescaler 35 from (P+1) to P. Next,the N counter 37 counts the output signal Fo of the voltage controloscillator 27, which has been P frequency-divided, at (N−A) times andthen outputs a pulse to the phase comparator 24 and the moduluscontroller 38. In response to this, the frequency division number of theprescaler 35 is changed to (P+1).

The frequency division number of the output signal Fo of the voltagecontrol oscillator 27 is (P+1)×A until the A counter 36 outputs anoutput and is P×(N−A) until the N counter 37 outputs an output.Therefore, if respective frequencies of an output signal and a referencesignal are assumed to be Fo and Fref, the following equation holds.$\begin{matrix}\begin{matrix}{{Fo} = {\left( {{\left( {P + 1} \right) \times A} + {P \times \left( {N - A} \right)}} \right) \times {Fref}}} \\{= {\left( {{P \times N} + A} \right) \times {Fref}}}\end{matrix} & \left\lbrack {{Equation}\quad 1} \right\rbrack\end{matrix}$Even when P=2^(n) (n is an integer), the number of available bands canbe increased by changing A in Equation 1.

To further increase the number of available bands, the ΔΣ modulator 33is provided. Moreover, to dissolve the spurious problem, the digitaldither circuit 32 is provided between the latch 31 and the ΔΣ modulator33. The latch 31 holds given frequency division data DATA. Note that inFIG. 2, CLOCK denotes a clock signal and STROBE denotes a strobe signal.The frequency division data DATA includes a digital value M representinginteger part and a digital value F representing fraction part(non-integer part). The F value is an n bit binary data. The digitaldither circuit 32 receives the F value from the latch 31 and supplies adigital output which has been discretely changed from the F value and ofwhich the time average corresponds to the F value or the F value as itis to the ΔΣ modulator 33 according to a SELECT signal. Specifically,when the SELECT signal is low, the F value, as it is, is supplied to theΔΣ modulator 33. When the SELECT signal is high, the digital output tobe supplied to the ΔΣ modulator 33 is periodically changed to F+k or F−k(k is an integer, e.g., 1). Then, based on an M value given by the latch31 and the output of the ΔΣ modulator 33, fractional frequency divisionby the prescaler 35, the A counter 36 and the N counter 37 is executed.As a result, whether or not the SELECT signal exists, the followingequation holds.Fo=((P×N+A)+F/2^(n))×Fref  [Equation 2]Thus, an output frequency step size equal to Fref×(F/2^(n)) is achieved.That is, in a normal operation state, an average frequency Fo of anoutput signal can be changed with a smaller step size than the frequencyFref of the reference signal, so that the reference frequency Fref canbe set at a large level. Thus, a PLL frequency synthesizer havingexcellent lockup characteristics can be obtained.

<The Internal Configuration and Operation of the Digital Dither Circuit32>

FIG. 3 is a block diagram illustrating the internal configuration of thedigital dither circuit 32 of FIG. 2. Referring to FIG. 3, the digitaldither circuit 32 includes a ½ frequency divider 41, selectors 42 and45, an adder 43, and a selection circuit 44.

The selection circuit 44 outputs Fdiv as EFdiv when the SELECT signal ishigh, and outputs a fixed value as EFdiv when the SELECT signal is low.

The ½ frequency divider 41 generates a clock signal DFdiv having a halffrequency of a frequency of the comparative signal EFdiv from theselection circuit 44.

The selector 42 receives a clock signal DFdiv from the ½ frequencydivider 41 at an S input, and selects a positive constant value or anegative constant value alternately in a manner in which a positivecohstant value [+k (A input)] is selected when the logic level of the Sinput is low, and a negative constant value [−k (13 input)] is selectedwhen the logic level of the S input is high.

The adder 43 receives the F value from the latch 31 at the A input andthe constant value [±k] from the selector 42 at the B input, andperforms addition operation A+B when a rise pulse of the comparatorsignal EFdiv is given as a CK input to periodically change a Y output toF+k or F−k.

The selector 45 receives the F value from the latch 31 at the A input,the Y output from the adder 43 at the B input, and the SELECT signal atthe S input. The selector 45 selects the F value (A input) when thelogic level of the S signal, i.e., the SELECT signal is low, and selectsas the Y output the Y output (B input) of the adder 43 when the logiclevel of the SELECT signal is high.

As has been described, the Y output of the selector 45, i.e., F+k or Fis finally supplied to the ΔΣ modulator 33 by the SELECT signal. Changeof the SELECT signal will be described later. FIGS. 4(a) and 4(b)illustrate the operation of the digital dither circuit 32.

<Simulation Results for Quantization Noise>

FIG. 5 is a graph showing simulation results for quantization noise inthe ΔΣ modulation fractional frequency division PLL frequencysynthesizer of FIG. 2. In this case, assuming that Fref=6.5 MHz, M=778,F=128, n=8, and k=1, a second order two-stage modulator is used as theΔΣ modulator 33.

From FIG. 5, it can be seen that frequency-response characteristics ofquantization noise are inclined and quantization noise in the lowfrequency band is reduced, compared to the case where no ΔΣ modulationis executed. The time average of frequency division number in thefractional frequency divider 28 is 778.5, which totally corresponds to adesired frequency division number. Furthermore, no concentration ofquantization noise in a particular frequency number is not caused. If itis taken into consideration that when the digital dither circuit 32 isnot provided and the F value (=128=27), as it is, is given to the ΔΣmodulator 33, a large spectrum appears around 800 kHz, great effects ofthe digital dither circuit 32 can be achieved.

<Modified Example>

Note that the configuration of the digital dither circuit 32 is notlimited to that of FIG. 3. The digital dither circuit 32 may have acircuit configuration in which according to the given F value, (1) the Fvalue as it is or (2) a value which has been obtained by randomlyobtaining F+k and F−k in unspecific periodical intervals and of whichthe time average corresponds to the time average of the F value istransmitted to the ΔΣ modulator 33.

<SELECT Signal Change>

SELECT signal change is performed so as to randomly obtain F+k and F−kin unspecific periodical intervals and output a digital signal of whichthe time average corresponds to the F value to the ΔΣ modulator 33 onlywhen the F value is a particular value (e.g., F=2^(n−1), 2^(n−2) and soon), and the F value itself to the ΔΣ modulator 33 when the F value is avalue other than the particular value in order to suppress spuriouswhich occurs as a result of concentration of quantization noise in aparticular frequency. Specifically, the SELECT signal is changed to behigh when the given F value is a particular value and the SELECT signalis changed to low when the given F value is a value other than theparticular value. As a result, the digital dither circuit 32 outputs adigital value which has been discretely changed from the F value and ofwhich the time average corresponds to the F value to the ΔΣ modulator 33only when the given F value is the particular value (e.g., F=2^(n−1),2^(n−2) and so on), and outputs the F value, as it is, to the ΔΣmodulator 33 when the given F value is a value other than the particularvalue. Thus, the generation of spurious to an output of the voltagecontrol oscillator 27 in a particular frequency division ration issuppressed, so that the same characteristics as those of the known ΔΣmodulation D/A converter can be achieved in a frequency division ratioother than the particular frequency division ratio.

<The Configuration of a ΔΣ Modulation D/A Converter>

FIG. 6 illustrates an exemplary configuration of a ΔΣ modulation D/Aconverter according to the present invention. A ΔΣ modulation D/Aconverter 50 shown in FIG. 6 is a ΔΣ modulation D/A converter obtainedby additionally providing the digital dither circuit 32, for example,having the same configuration of FIG. 3 in the previous stage of theknown D/A converter including a ΔΣ modulator 51 and an integrator 52.The ΔΣ modulator 51 includes an adder 61, a 1 bit D/A converter 62, asubtracter 63, and a delayer 64. The integrator 52 is filter means forremoving quantization noise contained in an output of the ΔΣ modulator51 to obtain a desired analog output, and is also called “postfilter”.The digital dither circuit 32 is provided between a digital input andthe ΔΣ modulator 51 and selectively supplies a digital signal which hasbeen discretely changed from the digital input F and of which the timeaverage corresponds to the digital input F or the digital input F as itis to the ΔΣ modulator 51, according to the SELECT signal. Note that aclock signal to be supplied to each member is not shown.

With the ΔΣ modulation D/A converter 50 of FIG. 6, even if the bit widthof the digital input F of the ΔΣ modulator 51 is not increased, aspurious problem depending on the digital input F of the ΔΣ modulator 51can be dissolved.

1. A signal processing device characterized by comprising: a delta-sigmamodulator; and a digital dither circuit, provided between the digitalinput and the delta-sigma modulator, for selectively supplying to thedelta-sigma modulator a digital output which has been discretely changedfrom a digital input and of which a time average corresponds to thedigital input or the digital input, according to a value for the digitalinput.
 2. The signal processing device of claim 1, characterized in thatthe delta-sigma modulator supplies the digital output which has beendiscretely changed from the digital input and of which a time averagecorresponds to the digital input when the digital input is a particularvalue, and supplies the digital input to the delta-sigma modulator whenthe digital input is a value other than the particular value.
 3. Thesignal processing device of claim 1, characterized in that the digitaldither circuit supplies, as the digital output which has been discretelychanged from the digital input and of which a time average correspondsto the digital input, a signal which periodically changes to F+k or F−k(where F is a value for the digital input and k is an integer) to thedelta-sigma modulator.
 4. The signal processing device of claim 3,characterized in that k is
 1. 5. A signal processing methodcharacterized in that when a given digital input is a particular value,a digital output which has been discretely changed from the digitalinput and of which a time average corresponds to the digital input issupplied to a delta-sigma modulator, and when the digital input is avalue other than the particular value, the digital input is supplied tothe delta-sigma modulator.
 6. A delta-sigma modulation type fractionalfrequency division PLL frequency synthesizer which includes a phaselocked loop (PLL) having a fractional frequency divider, the synthesizercharacterized in that the fractional frequency divider includes a latchfor holding given division data, a delta-sigma modulator, a digitaldither circuit, provided between the latch and the delta-sigmamodulator, for receiving a digital input representing fraction part ofthe frequency division data from the latch and selectively supplying tothe delta-sigma modulator a digital output which has been discretelychanged from the digital input and of which a time average correspondsto the digital output or the digital input, according to a value for thedigital input, and circuit means for executing a fractional frequencydivision based on integer part of the frequency division data and anoutput of the delta-sigma modulator.
 7. The delta-sigma modulation typefractional frequency division PLL frequency synthesizer of claim 6,characterized in that the digital dither circuit includes a ½ frequencydivider for generating a clock signal having a half frequency of afrequency of an output signal of the fractional frequency divider, afirst selector for alternately selecting, where an integral value is k,a positive constant value [+k] or a negative constant value [−k], inresponse to a logic level change of a clock signal from the ½ frequencydivider, an adder for adding a value for a digital input from the latchcircuit and a constant value selected by the selector, and a secondselector for outputting a result from the addition by the adder when avalue for a digital input from the latch circuit is a particular valueand outputting a digital input from the latch circuit when a value of adigital input from the latch circuit is a value other than theparticular value.
 8. A radio communication device characterized bycomprising the delta-sigma modulation type fractional frequency divisionPLL frequency synthesizer of claim
 6. 9. A delta-sigma modulation typeD/A converter characterized by comprising: a delta-sigma modulator; adigital dither circuit, provided between the digital input and thedelta-sigma modulator, for selectively supplying to the delta-sigmamodulator a digital output which has been discretely changed from adigital input and of which a time average corresponds to the digitalinput or the digital input, according to a value for the digital input;and filter means for removing quantization noise contained in an outputof the delta-sigma modulator to obtain a desired analog output.